Most computing systems employ virtual memory techniques in order to create a larger memory space than the actual physical memory. The virtual address space is partitioned into contiguous blocks of virtual memory called pages. Each page is referenced by a virtual address which has a corresponding physical address. A page table is used to store the correspondence between a virtual address and its related physical page.
Due to its size, the page table is often stored in main memory. In some systems, portions of the page table can be stored in a specialized cache memory termed a translation lookaside buffer (TLB). When a processor requests a particular virtual address, the TLB is searched first for the corresponding physical address instead of accessing the page table in main memory. If the entry is in the TLB (otherwise termed a TLB hit), the physical address is retrieved and used to access memory. If the TLB does not contain the desired virtual address, a TLB miss occurs, and the desired translation is obtained from the page table, or the operating system's fault handler, and inserted into the TLB. A TLB miss, however, takes a significantly longer time thereby degrading the processor's performance.